This invention relates to a processing unit such as the integer unit of a reduced-instruction-set-computer (referred to below as a RISC processor), more particularly to a processing unit that can execute machine-language instructions comprising both an arithmetic or logic operation and a data transfer.
Statements involving both an arithmetic operation and a data transfer abound in, for example, the widely used C programming language. Two examples follow: EQU x=++y (1) EQU x=y++ (2)
Example (1) includes a prefix increment operation: first the value of y is incremented, then the incremented value is assigned to x. In example (2) incrementation is a suffix operation: first the value of y is assigned to x, then y itself is incremented.
When these statements are executed by, for example, a prior-art RISC processor, the values of x and y are stored in registers. Execution of the statement requires two machine-language instructions: one to increment the register containing the value of y, and one to transfer the original or incremented value to the register containing the value of x. Each machine-language instruction executes in one clock cycle, so the entire operation takes two clock cycles.
Data transfers preceded or followed by arithmetic and logic operations like these are extremely common in computer programs. It would be desirable to have a processing unit capable of executing such transfer-and-operation combinations more rapidly: in just one clock cycle, for example.